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dual port , xpressview , 225 mhz hdmi receiver data sheet adv7612 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog. com fax: 781.461.3113 ? 2010 C 2012 analog devices, inc. all rights reserved. features high - definition multimedia interface (hdmi ? ) 1.4a features supported all m andatory and additional 3d v ideo format s suppor ted extended colorimetry, including sycc601 , adobe rgb, adobe ycc 601 , xvycc extended gamut color cec 1.4 - compatible hdmi rece iver 225 mhz maximum tmds clock frequency xpressview fast s witching of hdmi ports 36- /30 - bit d eep c olor and 24 - bit color support high - bandwidth d igital content protection (hdcp) 1.4 support with internal hdcp keys hdcp r epeater s upport up to 127 ksvs supp orted integrated cec c ontroller programmable hdmi equalizer 5 v detect and h ot p lug assert for each hdmi port audio support audio support including high bit rate (hbr) and direct stream digital ( dsd ) s/pdif (iec 60958 - compatible) digital audio support supp orts up to four i 2 s outputs advance d audio mute feature dedicated, flexible audio output port super a udio cd (sacd) with dsd output interface hbr audio dolby ? truehd dts - hd master audio ? general interrupt controller with two interrupt outputs standard id entification (stdi) circuit highly flexible 36 - bit pixel output interface internal edid ram a ny - to - any 3 3 color space conversion (csc) matrix 2- layer pcb design supported 100- lead lqfp_ep, 14 mm 1 4 mm package qualified for automotive applications appl ications projectors automotive video conferencing hdtv s avr, htib soundbar s video switch es functional block dia gram hs/vs 4 i 2 s s/pdif hdcp keys fast switch tmds ddc hdmi1 tmds ddc hdmi2 deep color hdmi rx adv7612 component processor 36 5 output mux field/de llc data mclk hbr dsd sclk lrclk audio output mclk sclk output mux 36-bit ycbcr/rgb hs vs/field de llc 09308-001 notes 1. lrclk is accessible through the ap5 pin. figure 1.
adv7612 data sheet rev. d | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 general description ......................................................................... 3 detailed functional block diagram .......................................... 3 specifications ..................................................................................... 4 electrical characteristics ............................................................. 4 data and i 2 c timing characteristics ......................................... 5 absolute maximum ratings ............................................................ 7 package thermal performance ................................................... 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 power supply sequencing .............................................................. 11 power - up sequence ................................................................... 11 power - down sequence .............................................................. 11 functional overview ...................................................................... 12 hdmi receiver ........................................................................... 12 component processor ............................................................... 12 other features ............................................................................ 12 pixel input/output formatting .................................................... 13 pixel data output modes features .......................................... 13 outline dimensions ....................................................................... 17 ordering guide .......................................................................... 17 automotive products ................................................................. 17 revision history 5 /12 rev. c to rev. d changes to features section ............................................................ 1 changes to general description section and figure 2 ............... 3 added endnote 3 (table 1) ............................................................. 4 deleted tdm serial timing parameter ( table 2 ) ........................ 5 changes to figure 5 .......................................................................... 6 deleted figure 6 ................................................................................ 7 change d pin 75 to ap1 in figure 7 and table 4 ........................... 9 change d pin 89 and pin 90 descriptions (table 4) ................... 10 change s to hdmi receiver and other features sections ........ 12 deleted time - division multiplexed (tdm) mode section and figure 9 ..................................................................................... 13 added endnote 1 in pixel input/output formatting section and endnote 1 to table 5 ....................................................................... 15 changes to ordering guide .......................................................... 18 6/11 rev. b to rev. c changes to figure 7 .......................................................................... 9 updated outline dimensions ....................................................... 19 6/11 rev. a to rev. b changes to data output transition time (t 11 ), table 2 .............. 5 changes to pin 17 and pin 18 description, table 4 ................... 10 changes to pin 87 and pin 89 description, table 4 ................... 11 4 /11 rev. 0 to rev. a changes to features section ............................................................ 1 changes to order ing guide .......................................................... 19 added automotive products section ........................................... 19 11/10 revision 0: initial version
data sheet adv7612 rev. d | page 3 of 20 general description the adv7612 is offered in automotive, professional (no hdcp), and industrial versions. the operating temperature range is ?40c to +85c. the ug-216 contains critical information that must be used in conjunction with the adv7612. the adv7612 is a high quality xpressview? fast switching hdmi?-capable receiver. it incorporates a dual input hdmi- capable receiver that supports all mandatory 3d tv formats defined in hdmi 1.4a specification, hdtv formats up to 1080p 36-bit deep color, and display resolutions up to uxga (1600 1200 at 60 hz). it integrates a cec controller that supports the capability discovery and control (cdc) feature. the adv7612 incorporates xpressview fast switching on both input hdmi ports. using analog devices, inc., hardware-based hdcp engine that minimizes software overhead, xpressview technology allows fast switching between both hdmi input ports in less than 1 second. each hdmi port has dedicated 5 v detect and hot plug? assert pins. the hdmi receiver also includes an integrated program- mable equalizer that ensures robust operation of the interface with long cables. the adv7612 offers a flexible audio output port for audio data extraction from the hdmi stream. hdmi audio formats, including sacd via dsd and hbr, are supported by adv7612. the hdmi receiver has advanced audio functionality, such as a mute controller that prevents audible extraneous noise in the audio output. the adv7612 contains one main component processor (cp) that processes the video signals from the hdmi receiver. it provides features such as contrast, brightness and saturation adjustments, stdi detection block, free run, and synchronization alignment controls. fabricated in an advanced cmos process, the adv7612 is provided in a 14 mm 14 mm, 100-lead surface-mount lqfp_ep, rohs-compliant package, and is specified over the ?40c to +85c temperature range. detailed functional block diagram control interface i 2 c control and data pll edid repeater controller hdcp engine packet/ infoframe memory 12 12 12 backend color space conversion output formatter component processor 5v detect and hpd controller audio processor data preprocesor and color space conversion hdmi processor packet processor a b c mute interrupt controller (int1, int2) p0 to p11 * int2 can be only output on one of the pins: sclk/int2, mclk/int2, or hpa_a/int2. xtalp xtaln scl sda cs cec rxb_5v rxa_5v hpa_a/int2* hpa_b ddca_sda ddca_scl ddcb_sda ddcb_scl rxa_c rxb_c rxa_0 rxa_1 rxa_2 p12 to p23 p24 to p25 llc hs vs/field/alsb de int1 int2* ap1 ap5 sclk/int2* mclk/int2* ap0 ap2 ap3 ap4 audio output formatter hdcp eeprom equalizer sampler rxb_0 rxb_1 rxb_2 sampler equalizer dpll cec controller adv7612 xpressview ? fast switching 09308-002 figure 2. detailed functional block diagram
adv7612 data sheet rev. d | page 4 of 20 specifications at d vdd = 1.7 1 v to 1.8 9 v, dvddio = 3.14 v to 3.46 v, pvdd = 1.71 v to 1.89 v, tvdd = 3.14 v to 3.46 v, cvdd = 1.71 v to 1.89 v, operating temperature range, unless otherwise noted. electrica l characteristics table 1. parameter symbol test conditions /comments min typ max unit digital inputs 1 input high voltage v ih xtaln and xtalp 1.2 v v ih other digital inputs 2 v input low voltage v il xtaln and xtalp 0 .4 v v il other digital inputs 0.8 v input current i in reset pin 45 60 a cs pin 45 60 a other digital inputs 10 a input capacitance c in 10 pf digital inputs (5 v tolerant) 1 , 2 input high voltage v ih 2.6 v input low voltage v il 0.8 v input current i in ? 82 +82 a digital outputs 1 output high voltage v oh 2.4 v output low voltage v ol 0.4 v high impedance leakage current i leak vs/field/alsb pin 35 60 a hpa_a/int2, hpa_b pin 82 a digital inputs oth er than xtaln and x talp 10 a output capacitance c out 20 pf power requirements 3 , 4 digital core power supply d vdd 1.7 1 1.8 1.8 9 v digital i/o power supply dvddio 3.14 3.3 3.46 v pll power supply pvdd 1.71 1.8 1.89 v terminator power sup ply tvdd 3.14 3.3 3.46 v comparator power supply cvdd 1.71 1.8 1.89 v digital core supply current i dv dd dual 1080p60 12 bit with bg 5 port 149.5 201.9 ma digital i/o supply current i dvddio dual 1080p60 12 bit with bg 5 po rt 9.9 178.5 ma pll supply current i pvdd dual 1080p60 12 bit with bg 5 port 39.2 36.9 ma terminator supply current i tvdd dual 1080p60 12 bit with bg 5 port 121.4 134.5 ma comparator supply current i cvdd dual 1080p60 12 bit with bg 5 port 187.0 210.9 ma p ower - down c urrents 3 , 6 digital core supply current i dv dd _pd 0.3 0.4 ma digital i/o supply current i dvd dio _pd 1.3 1.7 ma pll supply current i pvdd_pd 1.5 1.8 ma terminator supply current i tvdd _pd 0.1 0.3 ma comparator supply current i cvdd _pd 1.3 1.7 ma power - up time t pwrup 25 ms 1 data guaranteed by characterization . 2 the following pins are 5 v tolerant: ddca_scl, ddca_sda, ddcb_scl, ddcb_sda, rxa_5v, and rxb_5v. 3 data recorded during lab characterization 4 maximum current consumption values are recorded with maximum rated voltage supply levels, moirex video pattern, and at maximum rated temperature. 5 bg = background. 6 power - down mode 0 (io map, register 0x0c = 0x62), ring oscillator powered down (hdmi map, register 0x48 = 0x01), and ddc pads off ( hdmi map, re gister 0x73 = 0x03) .
data sheet adv7612 rev. d | page 5 of 20 data and i 2 c timing characteris tic s table 2. parameter symbol test conditions/comments min typ max unit clock and crystal crystal frequency, xtal p 28.63636 mhz crystal frequency stability 50 ppm llc frequency range 13.5 170 mhz i 2 c ports scl frequency 400 k hz scl minimum pulse width high 1 t 1 600 ns scl minimum pulse width low 1 t 2 1.3 s start condition hold time 1 t 3 600 ns start condition setup time 1 t 4 600 ns sda setup time 1 t 5 100 ns scl and sda rise time 1 t 6 300 ns scl and sda fall time 1 t 7 300 ns stop condition setup time 1 t 8 0.6 s reset feature reset pulse width 5 ms clock outputs llc mark - space ratio 1 t 9 :t 10 45:55 55:45 % duty cycle data and control outputs 2 data output transition t ime 1 t 11 end of valid data to negative clock edge 1.0 2.2 ns t 12 negative clock edge to start of valid data 0.0 0.3 ns i 2 s port, master mode sclk mark - space ratio 1 t 15 :t 16 45:5 5 55:45 % duty cycle lrclk data transition time 1 t 17 end of valid data to negative sclk edge 10 ns t 18 negative sclk edge to start of valid data 10 ns i 2 s data transition time 1 t 19 end of valid data to negative sclk edge 5 ns t 20 negative sclk edge to start of valid data 5 ns 1 data guaranteed by characterization. 2 with the dll block on output clock bypassed.
adv7612 data sheet rev. d | page 6 of 20 timing diagrams sda scl t 5 t 3 t 4 t 8 t 6 t 7 t 2 t 1 t 3 9308-003 figure 3. i 2 c timing t 9 llc t 11 t 12 t 10 p0 to p23, hs, v s/field/alsb, de 9308-004 figure 4. pixel port and control sdr output timing s c l k lrclk i 2 s left-justified mode msb msb ? 1 t 15 t 16 t 17 t 19 t 20 t 18 msb msb ? 1 lsb msb t 19 t 20 t 19 t 20 notes 1. lrclk is a signal accessible via ap5 pin. 2. i 2 s signals are accessible via the ap1 to ap4 pins. i 2 s right-justified mode i 2 s i 2 s mode 09308-005 figure 5. i 2 s timing
data sheet adv7612 rev. d | page 7 of 20 abs olute maximum ratings table 3 . parameter rating dvdd to gnd 2.2 v pvdd to gnd 2.2 v dvddio to gnd 4.0 v cvdd to gnd 2.2 v tvdd to gnd 4.0 v digital inputs voltage to gnd gnd ? 0.3 v to dvddio + 0.3 v 5 v tolerant digital inputs to gnd 1 5.3 v digital outputs voltage to gnd gnd ? 0.3 v to dvddio + 0.3 v x talp, x taln ? 0.3 v to pvdd + 0.3 v scl/sda data pins to dvddio dvddio ? 0.3 v to dvddio + 3.6 v maximum junction temperatu re (t j max ) 125 c storage temperature range ? 60 c to + 150 c infrared reflow soldering (20 sec) 260 c 1 the following inputs are 3.3 v inputs but are 5 v tolerant: ddca_scl, ddca_sda, ddcb_scl , and ddcb_sda. stresses above those listed under absolute ma ximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to abs olute maximum rating conditions for extended periods may affect device reliability. package thermal perf ormance to reduce power consumption when using the adv7612 , the user is advised to turn off the unused sections of the part. due to the printed circui t board ( pcb ) metal variation and , therefore , variation in pcb heat conductivity, the value of ja may differ for various pcbs. the most efficient measurement solution is obtained using the package surface temperature to estimate the die temperature becau se this eliminates the variance associated with the ja value. the maximum junction temperature (t j max ) of 125c must not be exceeded. the following equation calculates the junction tempera - ture using the measured package surface temperature and applies o nly when no heat sink is used on the device under test (dut): ( ) total jt s j wtt += where: t s is the package surface temperature (c). jt = 0.3c/w for the 100 -lead lqfp_ep . w total = ((pvdd i pvdd ) + (0.05 tvdd i tvdd ) + (cvdd i cvdd ) + ( d vdd i dvdd ) + (dvddio i dvddio )) where 0.05 is 5% of the tvdd power that is dissipated on the part itself. esd caution
adv7612 data sheet rev. d | page 8 of 20 pin configuration and fu nction descriptions pin 1 indicator 26 27 28 29 30 31 32 33 34 35 36 37 38 39 2 3 4 7 6 5 1 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23 24 25 11 74 73 72 69 70 71 75 68 67 66 64 63 62 61 60 59 58 57 56 55 54 53 52 51 65 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 adv7612 top view (not to scale) ap1 ap0 vs/field/alsb hs de dvddio p0 p1 p2 p3 p4 p5 p6 dvdd p7 p8 p9 p10 p11 p12 p13 dvddio p14 p15 p16 cvdd rxa_c? rxa_c+ tvdd rxa_0? rxa_0+ tvdd rxa_1? rxa_1+ tvdd rxa_2? rxa_2+ cvdd rxb_c? rxb_c+ tvdd rxb_0? rxb_0+ tvdd rxb_1? rxb_1+ tvdd rxb_2? rxb_2+ cvdd hpa_a/int2 rxa_5v ddca_sda ddca_scl hpa_b rxb_5v ddcb_sda ddcb_scl cec dvdd xtaln xtalp pvdd cs reset int1 sda scl dvdd mclk/int2 ap5 sclk/int2 ap4 ap3 ap2 nc p35 p34 dvddio p33 p32 p31 p30 p29 p28 p27 dvddio p26 p25 p24 dvdd llc p23 p22 p21 p20 p19 p18 p17 nc notes 1. nc = no connect. do not connect to this pin. 2. connect exposed pad (pin0) to gro und (bottom). 09308-008 figure 6. pin configuration table 4. pin function descriptions pin no. mnemonic type description 0 gnd ground ground. 1 cvdd power hdmi analog block supply voltage (1.8 v). 2 rxa_c? hdmi input digital input clock complement of port a in the hdmi interface. 3 rxa_c+ hdmi input digital input clock true of port a in the hdmi interface. 4 tvdd power terminator supply voltage (3.3 v). 5 rxa_0? hdmi input digital input channel 0 complement of port a in the hdmi interface. 6 rxa_0+ hdmi input digital input channel 0 true of port a in the hdmi interface. 7 tvdd power terminator supply voltage (3.3 v). 8 rxa_1? hdmi input digital input channel 1 complement of port a in the hdmi interface. 9 rxa_1+ hdmi input digital input channel 1 true of port a in the hdmi interface. 10 tvdd power terminator supply voltage (3.3 v). 11 rxa_2? hdmi input digital input channel 2 complement of port a in the hdmi interface. 12 rxa_2+ hdmi input digital input channel 2 true of port a in the hdmi interface. 13 cvdd power hdmi analog block supply voltage (1.8 v). 14 rxb_c? hdmi input digital input clock complement of port b in the hdmi interface.
data sheet adv7612 rev. d | page 9 of 20 pin no. mnemonic type description 15 rxb_c+ hdmi input digital input clock true of port b in the hdmi interface. 16 tvdd power terminator supply voltage (3.3 v). 17 rxb_0 ? hdmi input digital input channel 0 complement of port b in the hdmi interface. 18 rxb_0+ hdmi input digita l input channel 0 true of port b in the hdmi interface. 19 tvdd po wer terminator supply voltage (3.3 v). 20 rxb_1 ? hdmi input digital input channel 1 complement of port b in the hdmi interface. 21 rxb_1+ hdmi input digital input channel 1 true of port b in the hdmi interface. 22 tvdd power terminator supply voltage (3 .3 v). 23 rxb_2 ? hdmi input digital input channel 2 complement of port b in the hdmi interface. 24 rxb_2+ hdmi input digital input channel 2 true of port b in the hdmi interface. 25 cvdd power hdmi analog block supply voltage (1.8 v). 26 nc no connect no connect. 27 p35 digital video output video pixel output port. 28 p34 digital video output video pixel output port. 29 dvddio power digital i/o supply voltage (3.3 v). 30 p33 digital video output video pixel output port. 31 p32 digital video output video pixel output port. 32 p31 digital video output video pixel output port. 33 p30 digital video output video pixel output port. 34 p29 digital video output video pixel output port. 35 p28 digital video output video pixel output port. 36 p27 digital video output video pixel output port. 37 dvddio power digital i/o supply voltage (3.3 v). 38 p26 digital video output video pixel output port. 39 p25 digital video output video pixel output port. 40 p24 digital video output video pixel output port. 41 dvdd power digital core supply voltage (1.8 v). 42 llc digital video output line - locked output clock for the pixel data (range is 13.5 mhz to 170 mhz). 43 p23 digital video output video pixel output port. 44 p22 digital video output video pixel output port. 45 p21 digital video output video pixel output port. 46 p20 digital video output video pixel output port. 47 p19 digital video output video pixel output port. 48 p18 digital video output video pixel output port. 49 p17 digital video output vide o pixel output port. 50 nc no connect no connect. 51 p16 digital video output video pixel output port. 52 p15 digital video output video pixel output port. 53 p14 digital video output video pixel output port. 54 dvddio power digital i/o supply voltage (3.3 v). 55 p13 digital video output video pixel output port. 56 p12 digital video output video pixel output port. 57 p11 digital video output video pixel output port. 58 p10 digital video output video pixel output port. 59 p9 digital video output vi deo pixel output port. 60 p8 digital video output video pixel output port. 61 p7 digital video output video pixel output port. 62 dvdd power digital core supply voltage (1.8 v). 63 p6 digital video output video pixel output port. 64 p5 digital video o utput video pixel output port. 65 p4 digital video output video pixel output port.
adv7612 data sheet rev. d | page 10 of 20 pin no. mnemonic type description 66 p3 digital video output video pixel output port. 67 p2 digital video output video pixel output port. 68 p1 digital video output video pixel output port. 69 p0 digita l video output video pixel output port. 70 dvddio power digital i/o supply voltage (3.3 v). 71 de miscellaneous digital de (data enable) is a signal that indicates active pixel data. 72 hs digital video output hs is a horizontal synchronization output signal. 73 vs/field/alsb digital video output vs is a vertical synchronization output signal. field is a field synchronization output signal in all interlaced video modes. vs or field can be configured for this pin. alsb allows selection of the i 2 c addre ss. 74 ap0 miscellaneous digital audio output pin. pin ap0 to pin ap5 can be configured to output s/pdif digital a udio output, hbr , dsd , dst, or i 2 s. 75 ap1 miscellaneous digital audio o utput pin. pin ap0 to pin ap5 can be configured to output s/pdif di gital a udio o utput , hbr , dsd , dst, or i 2 s. 76 ap2 miscellaneous digital audio output pin. pin ap0 to pin ap5 can be configured to output s/pdif digital audio output , hbr , dsd , dst, or i 2 s. 77 ap3 miscellaneous ditial audio output pin. pin ap0 to pin ap5 can be configured to output s/pdif d igital a udio o utput , hbr , dsd , dst, or i 2 s. 78 ap4 miscellaneous ditial audio output pin. pin ap0 to pin ap5 can be configured to output s/pdif d igital a udio o utput , hbr , dsd , dst, or i 2 s. 79 sclk/int2 miscellaneous di gital a dual function pin that can be configured to output an a udio serial c lock or an interrupt 2 signal. 80 ap5 miscellaneous audio output pin. pin ap0 to pin ap5 can be configured to output s/pdif d igital a udio o utput , hbr , dsd , dst, or i 2 s. additiona lly , p in ap5 can be configured to provide lrclk. 81 mclk/int2 miscellaneous a dual fu n ction pin that can be configured to output an a udio m aster c lock or an interrupt 2 signal. 82 dvdd power digital core supply voltage (1.8 v). 83 scl miscellaneous dig ital i 2 c port serial clock input. scl is the clock line for the control port. 84 sda miscellaneous digital i 2 c port serial data input/output pin. sda is the data line for the control port. 85 int1 miscellaneous digital interrupt. this pin can be active low or active high. when status bits change, this pin is triggered. the events that trigger an interrupt are under user configuration. 86 reset miscellaneous digital system reset input. active low. a minimum low reset pulse width of 5 m s is required to reset the adv7612 circuitry. 87 cs miscellaneous digital chip select. this pin has an internal pull - down. pulling this line up cause s i 2 c state machine to ignore i 2 c transmission . 88 pvdd power pll supply voltage (1.8 v) . 89 x talp miscellaneous analog input pin for 28.63636 mhz crystal or an external 1.8 v, 28.63636 mhz clock oscillator source to clock the adv7612. 90 x taln miscellaneous analog crystal input. input pin for 28.63636 mhz crystal. this pin should be lef t unconnected if xtalp is driven with 1.8 v clock signal. 91 dvdd power digital core supply voltage (1.8 v). 92 cec digital input/output consumer electronic control channel. 93 ddcb_scl hdmi input hdcp slave serial clock port b. ddcb_scl is a 3.3 v inpu t that is 5 v tolerant. 94 ddcb_sda hdmi input hdcp slave serial data port b. ddcb_sda is a 3.3 v input that is 5 v tolerant. 95 rxb_5v hdmi input 5 v detect pin for port b in the hdmi interface. 96 hpa_b miscellaneous digital hot plug a ssert signal out put for hdmi p ort b. 97 ddca_scl hdmi input hdcp slave serial clock port a. ddca_scl is a 3.3 v input that is 5 v tolerant. 98 ddca_sda hdmi input hdcp slave serial data port a. ddca_sda is a 3.3 v input that is 5 v tolerant. 99 rxa_5v hdmi input 5 v detect pin for port a in the hdmi interface. 100 hpa_a/int2 miscellaneous digital a dual function pin that can be configured to output hot plug a ssert signal (for hdmi p ort a) or an interrupt 2 signal.
data sheet adv7612 rev. d | page 11 of 20 power supply sequencing power-up sequence the recommended power-up sequence of the adv7612 is to power up the 3.3 v supplies first, followed by the 1.8 v supplies. reset should be held low while the supplies are powered up. alternatively, the adv7612 may be powered up by asserting all supplies simultaneously. in this case, care must be taken while the supplies are being established to ensure that a lower rated supply does not go above a high er rated supply level. power-down sequence the adv7612 supplies may be de-asserted simultaneously as long as a higher rated supply does not go below a lower rated supply. 3.3v power supply (v) 1.8v 3.3v supplies 1.8v supplies 1.8v supplies power-up 3.3v supplies power-up 9308-007 figure 7. recommended power-up sequence
adv7612 data sheet rev. d | page 12 of 20 functional overview hdmi receiver the hdmi receiver supports all mandatory and many optional 3d formats, hdtv formats up to 1 080p, and all display resolutions up to uxga (1600 1200 at 60 hz). with the inclusion of hdcp, displays can now receive encrypted video content. the hdmi interface of the adv7612 allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during transmission , as specified by the hdcp 1. 4 protocol. the hdmi - compatible receiver on the adv7612 allows program - mable equalization of the hdmi data signals. this equalization compensates for the high frequency losses inherent in hdmi and dvi cabling, especially at longer lengths and higher frequencies. it is capable of equalizing for cable lengths up to 30 meters to achiev e robust receiver performance . the adv7612 has a synchr onization regener ation block used to regenerate the de based on the measurement of the video format being displayed, and to filter the horizontal and vertical synchronization signals to prevent glitches. the hdmi r eceiver also supports terc4 error detection, used for det ection of corrupted hdmi packet s following a cable disconnect . the hdmi receiver offers advanced audio functionality. the receiver contains an audio mute controller that can detect a variety of conditions , which may result in audible extraneous noise in th e audio output. on detection of these conditions, the audio signal can be ramped to prevent audio clicks or pops. audio output can be formatted to one of the following modes: ? l pcm and iec 61937 s/pdif ? dsd audio ? dst audio ? hbr audio xpressview fast switching can be implemented with full hdcp authentication available on the background port. sync hro - nization measurement and status information are available for the background port. hdmi receiver features include: ? 2 :1 multiplexed hdmi receiver ? 3d format support ? 225 mhz hdmi receiver ? integrated equalizer for cable lengths up to 30 meters ? hdcp 1. 4 also on background ports ? internal hdcp keys ? 36- /30 - bit d eep c olor support ? pcm, hbr, dst, and dsd audio packet support ? repeater support ? internal edid ram ? hot plug assert output pin for each hdmi port ? cec controller component processor the adv7612 has an any - to - any 3 3 csc matrix. the csc block is placed at the back of the cp section. csc enables yprpb -to- rgb and rgb - to - ycrcb conversions. many other standards of color sp ace can be implemented using the color space converter. cp features include: ? 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and many other hdtv formats are supported ? manual adjustments including gain (contrast) and offset (brightness), hue , and saturation ? f ree run output mode that provides stable timing when no video input is present ? 170 mhz conversion rate, which supports rgb input resolutions up to 1600 1200 at 60 hz ? contrast, brightness, hue, and saturation controls ? standard identification enabled by s tdi block ? rgb that can be color space converted to ycrcb and decima ted to a 4:2:2 format for video - centric back end ic interfacing ? de output signal supplied for direct connection to hdmi/dvi transmitter other features the adv7612 has hs, vs, field, and de output signals with programmable position, polarity, and width . the adv7612 has two programmable interrupt request output pins, including int1 and int2 (int2 is accessible only via one of following pins: mclk/int2 , sclk/int2 , or hpa_a/int2) . it also featu res a low power - down mode . the i 2 c address of the main map is 0x98 after reset. this can be changed after reset to 0x9a if pullup is attached to vs/field/alsb pin and i 2 c command sample_alsb is issued. refer to the register access and serial ports descrip tion section in the ug - 216. the adv7612 is provided in a 14 mm 14 mm, rohs - c ompliant lqfp_ep package, and is specified over the ?40 c to + 85 c temperature range.
data sheet adv7612 r ev. d | page 13 of 20 pixel input/output f ormatting the output section of the adv7612 is highly flexible. the pixel output bus can support up to 36 - bit 4:4:4 ycrcb or 36 - bit 4:4:4 rgb. the pixel data supports both single and double d ata rates modes 1 . in sdr mode, a 16 - /20 - /24 - bit 4:2:2 or 24 - /30 - /36 - bit 4:4:4 output is possible. in ddr mode, the pixel output port can be configured in an 8 - /10 - /12 - bit 4:2:2 ycrcb or 12 - bit 4:4:4 rgb. bus rotation is supported. table 5 to table 8 outline the different output formats that are supported. all output modes are controlled via i 2 c. 1 ddr mode is only supported only up to 50 mhz (an equivalent to data rate clocked 100 mhz clock in sdr mode). p ixel data output mod es features the output pixel port features include the following: ? 8- /10 - /1 2- bit itu - r bt.656 4:2:2 ycrcb with embedded time codes and/or hs, vs, and field output signals ? 16- /20 - /24 - bit ycrcb with embedded time codes and/or hs and vs/field pin timing ? 24- /30 - /36 - bit ycrcb/rgb with embedded time codes and/or hs and vs/field pin ti ming ? ddr 8 - /10 - /12 - bit 4:2 :2 ycrcb ? d dr 12 - /24 - /30 - /36 bit 4:4:4 rgb table 5 . sdr 4:2:2 output modes sdr 4:2:2 op_format_sel[7:0] 0x0 1 0x1 0x2 0x6 0x0a pixel output 8 - bit sdr itu - r bt.656 mode 0 10 - bit sdr itu - r bt.656 mode 0 1 2 - bit sdr itu - r bt.656 mode 0 12 - bit sdr itu - r bt.656 mode 1 12 - bit sdr itu - r bt.656 mode 2 p35 high -z high -z high -z high -z y3, cb3, cr3 p34 high -z high -z high -z high -z y2, cb2, cr2 p33 high -z high -z high -z high -z y1, cb1, cr1 p32 high -z high -z high -z high -z y0, cb0, cr0 p31 high -z high -z high -z high -z high -z p30 high -z high -z high -z high -z high -z p29 high -z high -z high -z y1, cb1, cr1 high -z p28 high -z high -z high -z y0, cb0, cr0 high -z p27 high -z high -z high -z high -z high -z p26 high -z high -z high -z high -z high -z p25 high -z high -z high -z high -z high -z p24 high -z high -z high -z high -z high -z p23 y7, cb7, cr7 y9, cb9, cr9 y11, cb11, cr11 y11, cb11, cr11 y11, cb11, cr11 p22 y6, cb6, cr6 y8, cb8, cr8 y10, cb10, cr10 y10, cb10, cr10 y10, cb10, cr10 p21 y5, cb5, cr5 y7, cb7, cr7 y9, cb9, cr9 y9, cb9, cr9 y9, cb9, cr9 p20 y4, cb4, cr4 y6, cb6, cr6 y8, cb8, cr8 y8, cb8, cr8 y8, cb8, cr8 p19 y3, cb3, cr3 y5, cb5, cr5 y7, cb7, cr7 y7, cb7, cr7 y7, cb7, cr7 p18 y2, cb2, cr2 y4, cb4, cr4 y6, cb6, cr6 y 6, cb6, cr6 y6, cb6, cr6 p17 y1, cb1, cr1 y3, cb3, cr3 y5, cb5, cr5 y5, cb5, cr5 y5, cb5, cr5 p16 y0, cb0, cr0 y2, cb2, cr2 y4, cb4, cr4 y4, cb4, cr4 y4, cb4, cr4 p15 high -z y1, cb1, cr1 y3, cb3, cr3 y3, cb3, cr3 high -z p14 high -z y0, cb0, cr0 y2, cb2, cr2 y2, cb2, cr2 high -z p13 high -z high -z y1, cb1, cr1 high -z high -z p12 high -z high -z y0, cb0, cr0 high -z high -z p11 high -z high -z high -z high -z high -z p10 high -z high -z high -z high -z high -z p9 high -z high -z high -z high -z high -z p8 high -z high -z high -z high -z high -z p7 high -z high -z high -z high -z high -z p6 high -z high -z high -z high -z high -z p5 high -z high -z high -z high -z high -z p4 high -z high -z high -z high -z high -z p3 high -z high -z high -z high -z high -z p2 high -z high -z high -z high -z high -z p1 high -z high -z high -z high -z high -z p 0 high - z high - z high - z high - z high - z 1 modes 0x00, 0x01, 0x02, 0x06 and 0x0a require additional writes to io map reg. 0x19[7:6]=2b11 and io map reg.0x33[6]=1
adv7612 data sheet rev. d | page 14 of 20 table 6 . sdr 4:2:2 and 4:4:4 output modes sdr 4:2:2 sdr 4:4:4 op_format_sel[7:0] 0x80 0x81 0x82 0x86 0x8a 0x40 0x41 0x42 0x46 pixel output 16- bit sdr it u- r bt.656 4:2:2 mode 0 20- bit sdr itu - r bt.656 4:2:2 mode 0 24 - bit sdr itu - r bt.656 4:2:2 mode 0 24 - bit sdr itu - r bt.656 4:2:2 mode 1 24 - bit sdr itu - r bt.656 4:2:2 mode 2 24- bit sdr 4:4:4 mode 0 30- bit sdr 4:4:4 mode 0 36- bit sdr 4:4:4 mode 0 36 - bit sd r 4:4:4 mode 1 p35 high -z high -z high -z high -z y3 r7 r9 r11 r9 p34 high -z high -z high -z high -z y2 r6 r8 r10 r8 p33 high -z high -z high -z cb1, cr1 y1 r5 r7 r9 r7 p32 high -z high -z high -z cb0, cr0 y0 r4 r6 r8 r6 p31 high -z high -z high -z high -z cb3, cr3 r3 r5 r7 r5 p30 high -z high -z high -z high -z cb2, cr2 r2 r4 r6 r4 p29 high -z high -z high -z y1 cb1, cr1 r1 r3 r5 r3 p28 high -z high -z high -z y0 cb0, cr0 r0 r2 r4 r2 p27 high -z high -z high -z high -z high -z high -z r1 r3 r1 p26 high -z high -z high -z high -z hi gh -z high -z r0 r2 r0 p25 high -z high -z high -z high -z high -z high -z high -z r1 g7 p24 high - z high - z high - z high - z high - z high - z high - z r0 g6 p23 y7 y9 y11 y11 y11 g7 g9 g11 g5 p22 y6 y8 y10 y10 y10 g6 g8 g10 g4 p21 y5 y7 y9 y9 y9 g5 g7 g9 g3 p20 y4 y6 y8 y8 y8 g4 g6 g8 g2 p19 y3 y5 y7 y7 y7 g3 g5 g7 g1 p18 y2 y4 y6 y6 y6 g2 g4 g6 g0 p17 y1 y3 y5 y5 y5 g1 g3 g5 b11 p16 y0 y2 y4 y4 y4 g0 g2 g4 b10 p15 high -z y1 y3 y3 high -z high -z g1 g3 b9 p14 high -z y0 y2 y2 high -z high -z g0 g2 b8 p13 high -z high -z y1 high -z high -z high -z high -z g1 g11 p12 high - z high - z y0 high - z high - z high - z high - z g0 g10 p11 cb7, cr7 cb9, cr9 cb11, cr11 cb11, cr11 cb11, cr11 b7 b9 b11 b7 p10 cb6, cr6 cb8, cr8 cb10, cr10 cb10, cr10 cb10, cr10 b6 b8 b10 b6 p9 cb5, cr5 cb7, cr7 cb9, cr9 cb9, cr9 cb9, cr9 b5 b7 b9 b5 p8 cb4, cr4 cb6, cr6 cb8, cr8 cb8, cr8 cb8, cr8 b4 b6 b8 b4 p7 cb3, cr3 cb5, cr5 cb7, cr7 cb7, cr7 cb7, cr7 b3 b5 b7 b3 p 6 cb2, cr2 cb4, cr4 cb6, cr6 cb6, cr6 cb6, cr6 b2 b4 b6 b2 p5 cb1, cr1 cb3, cr3 cb5, cr5 cb 5, cr5 cb5, cr5 b1 b3 b5 b1 p4 cb0, cr0 cb2, cr2 cb4, cr4 cb4, cr4 cb4, cr4 b0 b2 b4 b0 p3 high -z cb1, cr1 cb3, cr3 cb3, cr3 high -z high -z b1 b3 r11 p2 high -z cb0, cr0 cb2, cr2 cb2, cr2 high -z high -z b0 b2 r10 p1 high -z high -z cb1, cr1 high -z high -z hi gh -z high -z b1 g9 p0 high -z high -z cb0, cr0 high -z high -z high -z high -z b0 g8
data sheet adv7612 r ev. d | page 15 of 20 table 7 . ddr 4:2:2 output modes ddr 4:2:2 mode (clock/2) op_format_sel[7:0] 0x20 0x21 0x22 8- bit ddr itu - 656 (clock/2 output) 4:2:2 mode 0 10- bit ddr itu - 656 (clock/2 output) 4:2:2 mode 0 12- bit ddr itu - 656 (clock/2 output) 4:2:2 mode 0 pixel output clock rise clock fall clock rise clock fall clock rise clock fall p35 high -z high -z high -z high -z high -z high -z p34 high -z high -z high -z high -z high -z high -z p33 high -z high -z high -z high -z high -z high -z p32 high -z high -z high -z high -z high -z high -z p31 high -z high -z high -z high -z high -z high -z p30 high -z high -z high -z high -z high -z high -z p29 high -z high -z high -z high -z high -z high -z p28 high -z high -z high -z high -z high -z high -z p27 high -z high -z high -z high -z high -z high -z p26 high -z high -z high -z high -z high -z high -z p25 high - z high - z high - z high - z high - z high - z p24 high -z high -z high -z high -z high -z high -z p23 cb7, cr7 y7 cb9, cr9 y9 cb11, cr11 y11 p22 cb6, cr6 y6 cb8, cr8 y8 cb10, cr10 y10 p21 cb5, cr5 y5 cb7, cr7 y7 cb9, cr9 y9 p20 cb4, cr4 y4 cb6, cr6 y6 cb8, cr8 y8 p19 cb3, cr3 y3 cb5, cr5 y5 cb7, cr7 y7 p18 cb2, cr2 y2 cb4, cr4 y4 cb6, cr6 y6 p17 cb1, cr1 y1 cb3, cr3 y3 cb5, cr5 y5 p16 cb0, cr0 y0 cb2, cr2 y2 cb4, cr4 y4 p15 high -z high -z cb1, cr1 y1 cb3, cr3 y3 p14 high -z high -z cb0, cr0 y0 cb2, cr2 y2 p13 high -z high -z high -z high -z cb1, cr1 y1 p12 high -z high -z high -z high -z cb0, cr0 y0 p11 high -z high -z high -z h igh -z high -z high -z p10 high -z high -z high -z high -z high -z high -z p9 high -z high -z high -z high -z high -z high -z p 8 high - z high - z high - z high - z high - z high - z p7 high -z high -z high -z high -z high -z high -z p6 high -z high -z high -z high -z high -z high -z p5 h igh -z high -z high -z high -z high -z high -z p4 high -z high -z high -z high -z high -z high -z p3 high -z high -z high -z high -z high -z high -z p2 high -z high -z high -z high -z high -z high -z p1 high -z high -z high -z high -z high -z high -z p0 high -z high -z high -z high -z high -z high -z
adv7612 data sheet rev. d | page 16 of 20 table 8 . ddr 4:4:4 output modes ddr 4:4:4 mode (clock/2) 1 , 2 op_format_sel[7:0] 0x60 0x61 0x62 24 - bit ddr rgb ( clock /2 output) 30 - bit ddr rgb ( clock /2 output) 36 - bit ddr rgb ( clock /2 output) pixel outpu t clock rise clock fall clock rise clock fall clock rise clock fall p35 r7 -0 r7 -1 r9 -0 r9 -1 r11 -0 r11 -1 p34 r6 -0 r6 -1 r8 -0 r8 -1 r10 -0 r10 -1 p33 r5 -0 r5 -1 r7 -0 r7 -1 r9 -0 r9 -1 p32 r4 -0 r4 -1 r6 -0 r6 -1 r8 -0 r8 -1 p31 r3 - 0 r3 - 1 r5 - 0 r5 - 1 r7 - 0 r7 - 1 p30 r2 -0 r2 -1 r4 -0 r4 -1 r6 -0 r6 -1 p29 r1 -0 r1 -1 r3 -0 r3 -1 r5 -0 r5 -1 p28 r0 -0 r0 -1 r2 -0 r2 -1 r4 -0 r4 -1 p27 high -z high -z r1 -0 r1 -1 r3 -0 r3 -1 p26 high - z high - z r0 - 0 r0 - 1 r2 - 0 r2 - 1 p25 high -z high -z high -z high -z r1 -0 r1 -1 p24 high -z high -z high -z high -z r0 -0 r0-1 p23 g7 -0 g7 -1 g9 -0 g9 -1 g11 -0 g11 -1 p22 g6 -0 g6 -1 g8 -0 g8 -1 g10 -0 g10 -1 p21 g5 -0 g5 -1 g7 -0 g7 -1 g9 -0 g9 -1 p20 g4 -0 g4 -1 g6 -0 g6 -1 g8 -0 g8 -1 p19 g3 -0 g3 -1 g5 -0 g5 -1 g7 -0 g7 -1 p18 g2 - 0 g2 - 1 g4 - 0 g4 - 1 g6 - 0 g6 - 1 p17 g1 -0 g1 -1 g3 -0 g3 -1 g5 -0 g5 -1 p1 6 g0 -0 g0 -1 g2 -0 g2 -1 g4 -0 g4 -1 p15 high -z high -z g1 -0 g1 -1 g3 -0 g3 -1 p14 high -z high -z g0 -0 g0 -1 g2 -0 g2 -1 p13 high -z high -z high -z high -z g1 -0 g1 -1 p12 high -z high -z high -z high -z g0 -0 g0 -1 p11 b7 -0 b7 -1 b9 -0 b9 -1 b11 -0 b11 -1 p10 b6 -0 b6 -1 b8 -0 b8 -1 b10 -0 b10 -1 p9 b5 -0 b5 -1 b7 -0 b7 -1 b9 -0 b9 -1 p8 b4 -0 b4 -1 b6 -0 b6 -1 b8 -0 b8 -1 p7 b3 -0 b3 -1 b5 -0 b5 -1 b7 -0 b7 -1 p6 b2 -0 b2 -1 b4 -0 b4 -1 b6 -0 b6 -1 p5 b1 -0 b1 -1 b3 -0 b3 -1 b5 -0 b5 -1 p4 b0 -0 b0 -1 b2 -0 b2 -1 b4 -0 b4 -1 p3 high -z high -z b1 -0 b1 -1 b3 -0 b3 -1 p2 high -z high -z b0 -0 b0 -1 b2 -0 b2 -1 p1 high -z high -z high -z high -z b1 -0 b1 -1 p 0 high - z high - z high - z high - z b0 - 0 b0 - 1 1 - 0 = even samples. 2 - 1 = odd samples.
data sheet adv7612 rev. d | page 17 of 20 outline dimensions compliant to jedec standards ms-026-bed-hd top view (pins down) bottom view (pins up) exposed pad 1 1 25 25 26 26 50 50 76 76 100 100 75 75 51 51 0.27 0.22 0.17 0.50 bsc lead pitch pin 1 16.20 16.00 sq 15.80 14.20 14.00 sq 13.80 6.00 ref sq 12.00 bsc for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 06-22-2011-a 0.15 0.05 0.08 coplanarity 7 0 0.20 0.09 view a rotated 90 ccw 1.45 1.40 1.35 view a 1.60 max seating plane 0.75 0.60 0.45 1.00 ref figure 8. 100-lead low profile quad flat package [lqfp_ep] sw-100-2 dimensions shown in millimeters ordering guide model 1, 2, 3 temperature range package description package option adv7612bswz ?40c to +85c 100-lead lqfp_ep sw-100-2 ADV7612BSWZ-P ?40c to +85c 100-lead lqfp_ep sw-100-2 adv7612wbswz ?40c to +85c 100-lead lqfp_ep sw-100-2 eval-adv7612eb1z evaluation board with hdcp keys eval-adv7612eb2z evaluation board without hdcp keys eval-adv7612-7511 low cost evaluation board with hdcp eval-adv7612-7511p low cost evaluation board without hdcp 1 z = rohs compliant part. 2 the adv7612bsw z-p is a non-h dcp version. 3 w = qualified for auto motive applications. automotive products the adv7612wbswz model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. note that this automotive model may have specifications that differ from the commercial models; theref ore, designers should review the specifications section of this data sheet carefully. only the automotive grade product shown is ava ilable for use in automotive applications. contact your local analog devices account representative for specific product ordering informat ion and to obtain the specific automotive reliability reports for this model.
adv7612 data sheet rev. d | page 18 of 20 notes
data sheet adv7612 r ev. d | page 19 of 20 notes
adv7612 data sheet rev. d | page 20 of 20 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). hdmi, the hdmi logo, and high - definition multimedia interface are trademarks or registered tr ademarks of hdmi licensing llc in the united states and other countries. ? 2010 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09308 -0- 5 /12(d)

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